The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, it relates to a semiconductor device mixedly including an NMOS transistor and a PMOS transistor formed on a substrate and a method for fabricating the same.
In a general semiconductor device, both an NMOS transistor and a PMOS transistor are formed on one semiconductor substrate. In this case, it is necessary to implant n-type impurity ions alone in an n-type impurity diffusion layer and to implant p-type impurity ions alone in a p-type impurity diffusion layer. Therefore, the ion implantation should be performed with an NMOS transistor forming region and a PMOS transistor forming region alternately masked.
For example, Japanese Laid-Open Patent Publication No. 2003-100902 discloses a method for fabricating a semiconductor device mixedly including an NMOS transistor and a PMOS transistor formed on a substrate. In the method disclosed in this publication, a gate electrode of the NMOS transistor and a gate electrode of the PMOS transistor are formed respectively on an NMOS region and a PMOS region of the substrate. Then, offset spacers for covering the side faces of the gate electrodes are formed.
Next, after a first resist mask having an opening in the NMOS region is formed on the substrate, an n-type extension region is formed by selectively implanting an n-type impurity such as arsenic into the substrate. Then, after removing the first resist mask by ashing and cleaning, a second resist mask having an opening in the PMOS region is formed, and a p-type extension region is formed by selectively implanting a p-type impurity such as boron into the substrate.
Next, sidewalls are formed on the side faces of the offset spacers of the gate electrodes. Subsequently, a third resist mask for exposing an n-type transistor forming region is formed on the substrate, and n-type source/drain diffusion layers are formed by selectively implanting the n-type impurity into the substrate. Furthermore, after removing the third resist mask, a fourth resist mask for exposing a p-type transistor forming region is formed, and p-type source/drain diffusion layers are formed by selectively implanting the p-type impurity into the substrate. Thus, both the NMOS transistor and the PMOS transistor can be formed on the substrate.
In the conventional fabrication method, however, the PMOS region and the gate electrode of the PMOS transistor are doped with the n-type impurity such as arsenic in removing the first resist mask, so as to disadvantageously degrade the characteristics of the PMOS transistor.
In forming the n-type extension region, the n-type impurity such as arsenic is implanted also into the first resist mask. Since arsenic is a comparatively heavy element, the n-type impurity having been implanted into the first resist mask does not vaporize but is concentrated during the ashing, so as to ultimately diffuse into the PMOS region and the gate electrode of the PMOS transistor.
The p-type extension region is a shallow junction and hence is largely affected by merely a small amount of n-type impurity present in the vicinity of the surface of the PMOS region. As a result, there arises a problem that the threshold value of the PMOS transistor is varied or the operation characteristics thereof are degraded.
Also, in the case where a heavy element such as indium is used as the p-type impurity for forming the p-type extension region, a similar problem arises in the NMOS transistor. Specifically, the NMOS region and the gate electrode of the NMOS transistor are doped with the indium having been implanted into the second resist mask in removing the second resist mask, so as to disadvantageously degrade the characteristics of the NMOS transistor.